Electrically erasable (E.sup.2) cells are commonly used in programmable devices such as electrically erasable programmable read only memories (EEPROMs), programmable logic devices (PLDs) and the like. One such E.sup.2 cell may be modeled as separate high voltage and low voltage select transistors for respective program and read operations. Such a cell has become known as a "6-wire cell" because it includes six nodes for connection (i.e., six voltage terminals). A so-called "5-wire cell" is similar in design but has its program and read gates tied together. A detailed description of a conventional 6-wire cell may be found in U.S. Pat. No. 5,331,590, the entire disclosure of which is incorporated herein by reference.
A conventional 6-wire cell 10 is illustrated in FIG. 1A. In the figure, cell 10 is shown partially schematically and partially with reference to semiconductor region representations. Such an illustration is the means commonly used by those skilled in the relevant arts to communicate their ideas to one another and further facilitates a discussion of certain biasing characteristics which will be of interest with respect to the present invention. Cell 10 includes an electrically erasable and programmable transistor 12 which includes a floating gate, indicated by FG. A drain of transistor 12 is connected to terminal D of cell 10. Transistor 12 may be programmed to be either conductive (programmed) or non-conductive (erased) by applying appropriate voltages to its terminals and through the use of a program path of cell 10 which includes program select transistor 14.
The conduction of transistor 14 is controlled by a voltage V.sub.pg applied (or not) to the gate of transistor 14. As will be understood with reference to the detailed description below, the floating gate of transistor 12 includes a portion which is adjacent to a buried implant region. The buried implant region is separated from the floating gate by a tunnel oxide which permits the programming and/or erasing of transistor 12 using Fowler-Nordheim tunneling as is well known in the art. The capacitance which exists by virtue of this layout is illustrated as capacitor C1 in FIG. 1A.
The control gate function for transistor 12 is provided by the same buried implant over a second thin oxide region connected to a control gate terminal CG. The floating gate is separated from the control terminal CG by an oxide layer, thicker than the tunnel oxide, having a capacitance Cc. Capacitance Cc acts to couple voltages onto the floating gate from terminal CG.
Read operations for cell 10 are controlled using read select transistor 16, which is connected in a read path of cell 10 between transistor 12 and terminal S. A read control voltage V.sub.rg is applied to the gate of transistor 16 to facilitate read operations and the state of transistor 12 (conducting/programmed or non-conducting/erased) may be determined by measuring the current I.sub.read through the read path when V.sub.rg .apprxeq.3-6 V and V.sub.c =1-2 V.
For proper data retention, an erased cell should not lose electrons (charge loss) from the floating gate. Conversely, for a programmed cell the FG should not gain electrons (charge gain). Any charge loss or charge gain which might inevitably occur should not lead to a change in the threshold voltage of the cell (Vt shift) of significantly more than 300 mV.
FIG. 1A further illustrates conventional biasing voltages used during read operations for cell 10. As shown, during conventional read operations, no voltage is applied to the drain of the program select transistor 14 (i.e., VPG=0). further, V.sub.s =0 and V.sub.rg is raised to approximately Vcc (e.g., 3-6 V). The drain of transistor 12 is at approximately 1.5 V and the read current, I.sub.read, is controlled by V.sub.fg. Under these conditions, V.sub.fg is approximately 2.5-6 V (compared to Vfg.apprxeq.-1 to -4.5 V when the cell is erased) and the tunnel oxide is susceptible to conduction of tunneling currents from the buried implant region because the floating gate is biased positive. For a tunnel oxide of 80 .ANG. thickness, the oxide field is approximately 4-5 MV/cm, leading to a significant Fowler-Nordheim tunneling current. V.sub.fg is most positive for a programmed cell when V.sub.cg is positive, i.e., during a read operation. Thus, such conditions may lead to unacceptable charge gain, causing a V.sub.t shift of more than 0.3 V for a few cells 10 during continuous read operations (e.g., such as in dynamic burn-in, which typically lasts 500-2000 hrs at 135-165.degree. C. and V.sub.cg =V.sub.cg read).
FIG. 1B illustrates this shift in V.sub.t for some cells which may occur after continuous reads (e.g., as may be experienced during burn-in of a device which includes a number of cells 10). As shown, during some initial read operations, the distribution of threshold voltages V.sub.t for all of the cells 10 of a device (e.g., an EEPROM, PLD or the like) may be uniformly distributed about a nominal value. However, after a number of continuous read operations (e.g., during a burn-in), the distribution may become skewed, corresponding to a number of cells exhibiting a large V.sub.t shift (.DELTA.V.sub.t). FIG. 1C illustrates the corresponding shift in read current (.DELTA.I.sub.read) which may be experienced by a number of cells as a result of the shift in threshold voltages.
It would be desirable to avoid such threshold voltage shifts for E.sup.2 cells such as cell 10 because such shifts tend to have a negative impact on device speed and may also lead to functional failures of the cells.